Nalaganje...
System-on-chip test architectures: nanometer design for testability
| Glavni avtor: | |
|---|---|
| Drugi avtorji: | |
| Format: | Printed Book |
| Jezik: | English |
| Izdano: |
Boston
Morgan Kaufmann
2008
|
| Teme: |
UL
| Signatura: |
621.9 WAN |
|---|---|
| Kopija | Zaloga ni dosegljiva |