Á lódáil...
System-on-chip test architectures: nanometer design for testability
| Príomhúdar: | |
|---|---|
| Údair Eile: | |
| Formáid: | Printed Book |
| Teanga: | English |
| Foilsithe: |
Boston
Morgan Kaufmann
2008
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| Ábhair: |
UL
| Gairmuimhir: |
621.9 WAN |
|---|---|
| Cóip | Live Status Unavailable |