Routing congestion in VLSI circuits : estimation and optimization /

Bibliographische Detailangaben
1. Verfasser: Saxena, Prashant
Weitere Verfasser: Shelar, Rupesh S., Sapatnekar, Sachin S.
Format: Printed Book
Veröffentlicht: New York : Springer, c2007.
Schlagworte:
Integrated circuits
Routing (Computer network management)
Online Zugang:http://www.loc.gov/catdir/toc/fy0803/2006939848.html
http://www.loc.gov/catdir/enhancements/fy0824/2006939848-d.html
LEADER 01022cam a22002537a 4500
999 |c 242672  |d 242672 
020 |a 9780387300375 (cased) 
020 |a 0387300376 (cased) 
020 |a 9780387485508 (eISBN) 
020 |a 0387485503 (eISBN) 
082 0 4 |a 621.395  |b PRA 
100 1 |a Saxena, Prashant. 
245 1 0 |a Routing congestion in VLSI circuits :  |b estimation and optimization /  |c Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar. 
260 |a New York :  |b Springer,  |c c2007. 
300 |a xiv, 248 p. :  |b ill. ; 
504 |a Includes bibliographical references and index. 
650 0 |a Integrated circuits 
650 0 |a Routing (Computer network management) 
700 1 |a Shelar, Rupesh S. 
700 1 |a Sapatnekar, Sachin S., 
856 4 1 |u http://www.loc.gov/catdir/toc/fy0803/2006939848.html 
856 4 2 |u http://www.loc.gov/catdir/enhancements/fy0824/2006939848-d.html 
942 |c BK 
952 |0 0  |1 0  |4 0  |6 621_395000000000000_PRA  |7 0  |9 257690  |a DFS  |b DFS  |d 2019-12-23  |l 0  |o 621.395 PRA  |p DFS3446  |r 2019-12-23  |w 2019-12-23  |y BK 

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