APA Edition Citation

Uyemura, J. P. (2006). Chip design for submicron VLSI: CMOS layout and simulation. Ceanage Learning India.

Chicago Edition Citation

Uyemura, John P. Chip Design for Submicron VLSI: CMOS Layout and Simulation. New Delhi: Ceanage Learning India, 2006.

MLA Edition Citation

Uyemura, John P. Chip Design for Submicron VLSI: CMOS Layout and Simulation. Ceanage Learning India, 2006.