|
|
|
|
| LEADER |
00796nam a2200169Ia 4500 |
| 008 |
150624b xxu||||| |||| 00| 0 eng d |
| 020 |
|
|
|a 8120316827
|
| 020 |
|
|
|a 8120316827
|
| 082 |
|
|
|a 621.39732
|
| 100 |
|
|
|a Baker, R. Jacob
|
| 245 |
|
|
|a CMOS:
|b Circuit design, layout, and simulation /
|c R. Jacob Baker
|
| 260 |
|
|
|a New Delhi :
|b Prentice Hall,
|c 1998.
|
| 300 |
|
|
|a 902 p.
|
| 505 |
|
|
|a 1. Well 2. Metal layers 3. Active and poly layers 4. Mosfet 6. BSIM SPICE model 7. CMOS passive elements 8. Design verification with LASICKT 9. Analog MOSFET models 10. Digital model 11. Inverter 12. Static logic gates 13. TG and flip-flops 14.
|
| 942 |
|
|
|c TXT
|
| 999 |
|
|
|c 53753
|d 53753
|
| 952 |
|
|
|0 0
|1 0
|4 0
|6 621_397320000000000_BAK_C
|7 0
|9 53731
|a UL
|b UL
|c SEC
|d 2012-10-27
|l 0
|o 621.39732 BAK/C
|p 77056
|r 2012-10-27
|y TXT
|