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Chip design for submicron VLSI: CMOS layout and simulation
| Autor principal: | |
|---|---|
| Format: | Printed Book |
| Publicat: |
Canada
Cengage learning
2006
|
| Matèries: |
| LEADER | 00525nam a22001577a 4500 | ||
|---|---|---|---|
| 020 | |a 9788131501955 | ||
| 082 | |a 621.381 5 |b VYE/C | ||
| 100 | |a Vyemura, John P. | ||
| 245 | |a Chip design for submicron VLSI: CMOS layout and simulation | ||
| 260 | |a Canada |b Cengage learning |c 2006 | ||
| 300 | |a 411p. | ||
| 650 | |a Chip design | ||
| 650 | |a Engineering | ||
| 942 | |c BK | ||
| 999 | |c 34262 |d 34262 | ||
| 952 | |0 0 |1 0 |4 0 |6 621_381000000000000_5_VYEC |7 0 |8 Stack |9 36250 |a KUCL |b KUCL |c Stack |d 2015-08-13 |l 0 |o 621.381 5 VYE/C |p 31257 |r 2015-08-13 |w 2015-08-13 |y BK | ||