APA ציטוט

Vyemura, J. P. (2006). Chip design for submicron VLSI: CMOS layout and simulation. Cengage learning.

Chicago Edition Citation

Vyemura, John P. Chip Design for Submicron VLSI: CMOS Layout and Simulation. Canada: Cengage learning, 2006.

ציטוט MLA

Vyemura, John P. Chip Design for Submicron VLSI: CMOS Layout and Simulation. Cengage learning, 2006.