APA引文

Chip Design for Submicorn VLSI: CMOS Layout ad Simulation. Cengage learning.

Chicago Edition Citation

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

MLA引文

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

警告：這些引文格式不一定是100％准確.