APA Citatie

Chip Design for Submicorn VLSI: CMOS Layout ad Simulation. Cengage learning.

Chicago Style citaat

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

MLA citatie

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

Let op: Deze citaties zijn niet altijd 100% accuraat.