APA引用形式

Chip Design for Submicorn VLSI: CMOS Layout ad Simulation. Cengage learning.

シカゴスタイル引用形

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

MLA引用形式

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

警告: この引用は必ずしも正確ではありません.