APA način citiranja

Chip Design for Submicorn VLSI: CMOS Layout ad Simulation. Cengage learning.

Čikaški stil citiranja

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

MLA način citiranja

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.