एपीए उद्धरण

Chip Design for Submicorn VLSI: CMOS Layout ad Simulation. Cengage learning.

शिकागो स्टाइल उद्धरण

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

एमएलए उद्धरण

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.