APA-viite

Chip Design for Submicorn VLSI: CMOS Layout ad Simulation. Cengage learning.

Chicago-tyylinen lähdeviittaus

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

MLA-viite

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.