Dyfyniad APA

Chip Design for Submicorn VLSI: CMOS Layout ad Simulation. Cengage learning.

Dyfyniad Arddull Chicago

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

Dyfyniad MLA

Chip Design for Submicorn VLSI: CMOS Layout Ad Simulation. Cengage learning.

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