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00614 a2200181 4500 |
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20151026133209.0 |
| 008 |
130606b xxu||||| |||| 00| 0 eng d |
| 020 |
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|a 9788131732472
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| 100 |
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|a Prasanna Raj, Cyril
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| 245 |
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|a Fundamentals of HDL design
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| 260 |
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|b Pearson
|c 2011
|a New Delhi
|
| 300 |
|
|
|a 558p.
|
| 653 |
|
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|a Digital electronics
|
| 653 |
|
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|a Verilog - computer hardware description language
|
| 653 |
|
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|a Logic circuits - computer aided design
|
| 942 |
|
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|c BK
|6 _
|
| 999 |
|
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|c 65080
|d 65080
|
| 952 |
|
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|0 0
|1 0
|2 udc
|4 0
|6 _
|7 0
|9 77436
|a UL
|b UL
|d 2013-02-08
|g 0.00
|l 3
|p 00068928
|r 2015-04-25
|s 2015-04-22
|v 0.00
|w 2013-02-08
|y BK
|