एपीए उद्धरण

Wang, L., & Stround, C. E. T. (2008). System-on-chip test architectures: Nanometer design for testability. Morgan Kaufmann.

शिकागो स्टाइल उद्धरण

Wang, Laung-Terng, और Charles E. Touba Stround. System-on-chip Test Architectures: Nanometer Design for Testability. Boston: Morgan Kaufmann, 2008.

एमएलए उद्धरण

Wang, Laung-Terng, और Charles E. Touba Stround. System-on-chip Test Architectures: Nanometer Design for Testability. Morgan Kaufmann, 2008.