Dyfyniad APA

Wang, L., & Stround, C. E. T. (2008). System-on-chip test architectures: Nanometer design for testability. Morgan Kaufmann.

Dyfyniad Arddull Chicago

Wang, Laung-Terng, and Charles E. Touba Stround. System-on-chip Test Architectures: Nanometer Design for Testability. Boston: Morgan Kaufmann, 2008.

Dyfyniad MLA

Wang, Laung-Terng, and Charles E. Touba Stround. System-on-chip Test Architectures: Nanometer Design for Testability. Morgan Kaufmann, 2008.

Rhybudd: Mae'n bosib nad yw'r dyfyniadau hyn bob amser yn 100% cywir.