Wang, L., & Stround, C. E. T. (2008). System-on-chip test architectures: Nanometer design for testability. Morgan Kaufmann.
シカゴスタイル引用形Wang, Laung-Terng, , Charles E. Touba Stround. System-on-chip Test Architectures: Nanometer Design for Testability. Boston: Morgan Kaufmann, 2008.
MLA引用形式Wang, Laung-Terng, , Charles E. Touba Stround. System-on-chip Test Architectures: Nanometer Design for Testability. Morgan Kaufmann, 2008.
警告: この引用は必ずしも正確ではありません.